This invention relates to an equalized capacitance wiring method for facilitating the LSI (large scale integration) of data processing or communication systems.
Supply of clock signals to a logic circuit which includes one distributing gate and a plurality of flip-flops, and which is one portion of an LSI circuit, is carried out by feeding signals from an input terminal of the LSI circuit to each of the flip-flops via the distributing gate. Plural wirings formed on the LSI circuit for transmitting those clock signals can not be formed with identical patterns. A difference in a clock signal transmission delay time from the input terminal to each flip-flop of the LSI circuit, which is generally known as a clock skew occurs, consequently. It is indispensable, therefore, to minimize such a clock skew in order to realize a high-speed logical circuit with a shorter clock cycle time.
The delay time caused by the wiring in the LSI circuit is generally expressed by the following formula. EQU T.sub.pd =.alpha.CR+.beta.
wherein:
T.sub.pd represents a delay time, C is a capacitance value, R is an output resistance at a block terminal, and .alpha., .beta. are constants determined by C and R.
According to the above formula, T.sub.pd between circuits may be equalized by adjusting values of C and R.
Technology for speed compensation of a critical path or wiring which has the maximum transmission time of the clock and data signals in an LSI circuit by varying such resistance R to adjust the delay time was proposed by A. H. Dansky in the IBM Journal of Research and Development, Vol. 25, No. 3, May 1981, pp. 116-125 under the title of "Bipolar Circuit Design for a 5000--Circuit VLSI Gate Array". Referring to FIG. 3 of this paper, there are provided resistors of 8 k.OMEGA. in parallel in a basic circuit wherein the use of either one resistor or both resistors is selected depending on the delay time of the circuit to obtain two values of resistance, i.e. 4 k.OMEGA. and 8 k.OMEGA.. The layout of those two resistors is made so that the wiring of a power supply source contacts selected ones of the resistors placed on a predetermined wiring area. In such a layout, since electric wiring is achieved within a predefined area (referred to as a block hereinafter), the respective arranged positions of blocks and the wired results between those blocks are not affected at all by that wiring. Evaluation and compensation of a delay time can, therefore, be carried out as a step subsequent to wiring. However, it is necessary to incorporate resistors in the basic circuit in advance and the resistors therefore must be given certain values within a limited scope. Additionally, such resistors cannot be fine-adjusted when used for delay time compensation. Varying resistance also entails increment/decrement of power and, therefore, an excessive amount of power will be necessary when a high-speed LSI is to be realized.
Another technology was disclosed by M. Jenkins et al in their paper "PHILO--A VLSI Design System" pp. 163-169, presented at 19th Design Automation Conference in 1982. The paper concerns the technology of preparing plural types of replaceable blocks having different power values and delay time and selecting the optimal block after wiring. This technology is advantageous in that without paying any special technical considerations to the placement of the circuit elements and the wiring to be provided inside of the blocks, a delay time can be compensated in a subsequent step. However, since the number and types of blocks which must be prepared in advance, will inconveniently increase, a time difference in the above-mentioned fine-adjustment made for the blocks occurs as a practical matter. In practice, since there is a limit in the number of elements which can be mounted on an LSI circuit, the number of resistors necessary for fine-adjustment of the delay time cannot be mounted on the LSI circuit. This makes fine-adjustment of the delay time in signal transmission impossible.
An object of this invention is, therefore, to provide an equalized capacitance wiring method for LSI circuits free of afore-described defects.